MOS type transistors are a fundamental building block within integrated circuits. Consequently, there is a persistent push to make such devices smaller, faster, etc. The switching speed of a transistor is obviously an important characteristic since it dictates, at least in one respect, how fast the circuits which employ such devices operate. Presently, the switching speed of a transistor is not limited by the channel transit time (i.e., the time required for charge to be transported across the channel); instead, the switching speed is limited by the time required to charge and discharge the capacitances that exist between the device electrodes and between the interconnecting conductive lines and the substrate.
One way of appreciating the MOS transistor capacitances is through an exemplary cross section, as illustrated in prior art FIG. 1. The transistor, designated at reference numeral 10, includes a p-type region 12 (sometimes referred to as the body), such as a P-well in a CMOS type process. The body 12 has an n-type drain region 14 formed therein and a lightly doped drain extension region 16. Likewise, a source region 18 and a lightly doped source extension region 20 is formed in the body 12. As is well known in the art, the extension regions 16 and 20 often are used to help overcome short channel transistor effects as device dimensions continue to shrink. A doped polysilicon gate 22 overlies a thin gate oxide 24 which defines a channel region 26 therebeneath in the body 12.
An effective circuit diagram illustrating the various transistor capacitances is illustrated in prior art FIG. 2. As seen in prior art FIG. 2, capacitances exist between the various device electrodes and between the electrodes and the body region. The drain-to-body capacitance (C.sub.db) and the source-to-body capacitance (C.sub.sb) are illustrated in both prior art FIGS. 1 and 2 and are referred to often as junction capacitances. The value of the junction capacitances are a function of both the cross sectional area of the junctions as well as the doping concentrations of the regions, respectively.
One attempt to increase the performance of the transistor 10 of prior art FIG. 1 reduces the junction capacitances by forming the transistor on an insulating region. Such s a transistor device structure is called a silicon-on-insulator (SOI) device and is illustrated in prior art FIG. 3. The SOI transistor, designated at reference numeral 30, has components similar to the transistor 10 of prior art FIG. 1. In the SOI transistor 30, however, the body 12 is not formed in the bulk semiconductor material 12 as in FIG. 1, but rather overlies an insulating layer 32 such as silicon dioxide (SiO.sub.2). The insulating layer 32, in turn, overlies a bulk semiconductor material 34 or other type substrate.
The SOI transistor 30 provides several performance advantages over traditional bulk transistor devices. Initially, since each device can be completely isolated from one another (as opposed to sharing a common body), better individual device isolation is achieved, which prevents circuit latch-up conditions. In addition, since at least a portion of the drain region 14 and the source region 18 abut the insulating layer 34, the cross sectional area of the source/body and drain/body interfaces is reduced and thus the junction capacitance is significantly reduced.
In addition to the aforementioned junction capacitances, the MOS transistor 10 of prior art FIG. 1 exhibits a gate to source capacitance (C.sub.gs) and a gate to drain capacitance (C.sub.gd), as highlighted schematically in prior art FIG. 2. The gate to source capacitance (C.sub.gs) and the gate to drain capacitance (C.sub.gd) have magnitudes which are a function of the gate, drain and source electrodes, their relative spacing, and the insulative dielectric material therebetween. Similar to the other capacitances described supra, C.sub.gs and C.sub.gd negatively impact the switching speed of the MOS transistor. As clearly seen in the SOI cross section of prior art FIG. 3, the conventional SOI MOS transistor structure 30 does not reduce or otherwise affect C.sub.gs and C.sub.gd. Therefore although conventional SOI transistors such as the transistor 30 provide improvements in the junction capacitance of the device, other undesirable capacitances still exist and serve to negatively impact transistor performance.
The SOI transistor 30 of prior art FIG. 3 also has another performance disadvantage. The insulating layer 32 generally is thermally insulative compared to the semiconductor material surrounding the layer 32. Therefore, as the SOI transistor 30 operates, heat which would generally dissipate through the substrate 34 in conventional bulk transistor devices 10 tends to build up in the body region 12 of the device. As is well known by those skilled in the art, device heating can lead to device performance degradation parametrically or functionally and can disadvantageously precipitate reliability problems.
Another problem exhibited by conventional bulk transistors 10 and conventional SOI transistors 30 alike relates to a relatively high impedance power supply voltage distribution throughout circuits utilizing such devices. That is, positive and/or negative supply voltages (e.g., V.sub.DD and V.sub.SS) are typically utilized throughout various portions of an integrated circuit chip to power the chip as needed. Such supply voltages are often distributed to various locations about the chip on supply voltage buses. However, the conductivity of the buses is directly related to their size. Therefore in order to reduce the impedance of the buses to negligible levels, the buses must be very large, which can negatively impact the integrated circuit die size and/or make circuit layout substantially more difficult, which increases the die cost.
Since die sizes cannot be excessively large, the supply voltage buses exhibit a modest amount of impedance. In addition, the individual conductive lines which carry the supply voltage from the bus or rail to each device also exhibits an impedance, which negatively impacts circuit performance. Schematically, this phenomena may be modeled as illustrated in prior art FIGS. 4a and 4b. In FIG. 4a, two MOS transistors 50 and 52 are each connected to the positive supply voltage rail or bus at different locations on the semiconductor die. Because the supply voltage bus exhibits a non-zero impedance (illustrated R.sub.DD in prior art FIG. 4a), the magnitude of the supply voltage differs at different locations about the chip (V.sub.DD .noteq.V.sub.DD '). Similarly, negative supply voltages may also differ, as illustrated in prior art FIG. 4b (i.e., V.sub.SS .noteq.V.sub.SS ').
The impedance within the power supply distribution system on a chip has several negative consequences. For example, since different portions of the circuit have different power supply voltage magnitudes applied thereto, transistors will perform slightly differently across the chip. These differences may negatively impact the timing at which various transistors switch, etc. In addition, the impedance along the supply voltage buses result in undesirable power dissipation and "IR" heating within the chip.
Therefore there is a need in the art for a transistor structure and circuit which exhibit reduced capacitance, improved thermal management and improved power supply voltage distribution throughout the chip.